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combinational logic造句

"combinational logic"是什么意思   

例句與造句

  1. Design basis of combinational logic circuit
    組合邏輯電路設(shè)計基礎(chǔ)
  2. A combinational logic element having at least one input channel
    一種至少有一個輸入通道的組合邏輯元件。
  3. Combinational logic element
    組合邏輯組件
  4. Combinational logic circuit
    組合邏輯電路
  5. Combinational logic element
    組合邏輯元件
  6. It's difficult to find combinational logic in a sentence. 用combinational logic造句挺難的
  7. Finally , we study two applications of bdd . the first one is the fault detect of combinational logic circuits
    最后,研究了基于bdd的組合電路的故障檢測方法和基于bdd的網(wǎng)絡(luò)可靠度的計算方法等兩方面的應(yīng)用。
  8. Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description
    邏輯綜合的功能是對組合邏輯函數(shù)的描述進(jìn)行轉(zhuǎn)換和優(yōu)化,生成與邏輯功能描述等價的優(yōu)化的邏輯級純結(jié)構(gòu)描述。
  9. The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance
    仿真實驗結(jié)果證明了改進(jìn)演化算法對于實現(xiàn)函數(shù)級數(shù)字組合邏輯電路的硬件演化是可行的,并且提高了演化算法的演化效率和收斂性能。
  10. Digital design : binary system , boolean algebra , logic gates , simplification of boolean functions , combinational logic . analog design : amplifiers , frequency response , feedback , operational amplifier
    數(shù)位設(shè)計:二進(jìn)位制、布氏代數(shù)、邏輯閘、布氏函數(shù)的化簡、組合邏輯電路。類比設(shè)計:放大器、頻率響應(yīng)、反饋系統(tǒng)、運算放大器。
  11. Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of classicepglo chip of altera co . and the detailed analyses of typical examples are also given
    結(jié)合altera公司classicep610芯片的結(jié)構(gòu),研究了將演化算法應(yīng)用于函數(shù)級數(shù)字組合邏輯電路的硬件演化,并且對典型實例進(jìn)行了詳細(xì)分析。
  12. All the sequential and combinational logics , tested though the simulation under the specific software , are proved to meet the requirements of the design . it is a good reference for accomplishing the mca in practice
    這些時序邏輯和組合邏輯功能均通過專用開發(fā)軟件的仿真驗證,達(dá)到設(shè)計要求,對實際上完成脈沖幅度多道分析器具有重要的參考價值。
  13. In this paper we discuss mca circuit , the sequential logic for mca data collection , for the setting of the uld , lld and the gain of pga , as well as the combinational logic for decoding circuits of the computer interface , based on cpld
    本文詳細(xì)論述了利用cpld實現(xiàn)的脈沖幅度多道電路及其數(shù)據(jù)采集的時序控制邏輯、閾值設(shè)定和程控放大倍數(shù)設(shè)定的時序控制邏四川大學(xué)碩士學(xué)位論文輯、以及與計算機(jī)接口的譯碼電路等組合控制邏輯。
  14. 3 ) give the reduct algorithm and improved algorithm based on discernibility matrices . 4 ) give the algorithm of rules . 5 ) in this thesis , by using rs theory in the synthesis of combinational logic function , we can get minimal expression of logic function ; if by using rs theory in the rough control of boiler , we can get rough control rules
    對于前人提出的差別矩陣和差別函數(shù)的概念和定義,將其應(yīng)用于信息系統(tǒng)中,用差別函數(shù)得到了最小約簡,然后,通過研究差別矩陣和差別函數(shù)的構(gòu)造過程,提出了對差別矩陣降階和消元的策略,實例證明是有效的,起到了化簡差別矩陣和差別函數(shù)的目的; 4
  15. The quantum gate array is the natural quantum generalization of acyclic combinational logic " circuit " studied in conventional computational complexity theory . in 1995 , barenco showed that almost any two - bit gate is universal , so building a feasible two - bit logic gate is the first step to engineer a quantum computer . in principle , the quantum bit can be carried by any two states system
    在眾多的量子計算機(jī)模型中目前討論最廣泛的是量子計算機(jī)門組網(wǎng)絡(luò)模型,量子計算機(jī)門組網(wǎng)絡(luò)模型是經(jīng)典計算機(jī)門組網(wǎng)絡(luò)結(jié)構(gòu)的量子推廣,它是根基于barenco等人所證明的“一個兩比特受控操作和對單比特進(jìn)行任意操作的門可以構(gòu)成一個‘通用量子邏輯門組’ ”之上的。

相鄰詞匯

  1. "combinational"造句
  2. "combinational algorithm"造句
  3. "combinational circuit"造句
  4. "combinational design"造句
  5. "combinational function"造句
  6. "combinational logic circuit"造句
  7. "combinational logic circuits"造句
  8. "combinational logic element"造句
  9. "combinational logic function"造句
  10. "combinational logic gate"造句
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